Have to be reimplemented, if IO bit set feature is implemented. Compare differences in datasheets, for example ATMega16 and ATMega48, on CBI and SBI usage at IO registers, which have special behaviour, if bit will be set to 1
This device isn't completely implemented. There is no boot loader section support for >= ATMega88, only normal interrupt vector start address supported, incomplete usart registers (and maybe more ...)
This device isn't completely implemented. There is no boot loader section support for >= ATMega88, only normal interrupt vector start address supported, incomplete usart registers (and maybe more ...)
OpenDrain class is disabled for the moment. I think, this functionality, to "wrap" a normal pin isn't right implemented and could be made more clear. And maybe it is useless, because to handle easily by normal Pin class.
Replace the status register with an ordinary byte somewhere and simple inline access functions sN(), gN() to get/set flags. This should also make accesses faster.
Member SerialRxBasic::Step (bool &trueHwStep, SystemClockOffset *timeToNextStepIn_ns=0)
This is bug if frame format is different (eg 7 or 9 bits)
The implementation of Socket has to be cleaned. In the moment, the Socket implementation for MingW acts only as client, the unix implementation could act also as server, but is this necessary?
In multiple core simulations which uses also gdb with single stepping we need a other solution to fit the time accurate behaviour. Currently on a single step from gdb the simulation runs until the command is completly executed which is NOT correct. Some commands need up to 4 cycles and the actual implementation do up to 4 steps for one step so the other cores run slower then in normal operation. This is not a problem today because we are not able to run multiple cores with gdb but this will be implementated later. So this version is only made for running the regression tests and stepping in gdb. Normal operation/simulation is not affected. (taken over from systemclock.cpp, but to check!)