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00026 #ifndef HWEEPROM
00027 #define HWEEPROM
00028
00029 #include "rwmem.h"
00030 #include "hardware.h"
00031 #include "memory.h"
00032 #include "traceval.h"
00033 #include "irqsystem.h"
00034
00035 class HWEeprom: public Hardware, public Memory, public TraceValueRegister {
00036 protected:
00037 AvrDevice *core;
00038 unsigned int eear;
00039 unsigned int eear_mask;
00040 unsigned char eecr;
00041 unsigned char eecr_mask;
00042 unsigned char eedr;
00043 HWIrqSystem* irqSystem;
00044 unsigned int irqVectorNo;
00045 int opEnableCycles;
00046 int cpuHoldCycles;
00047 int opState;
00048 int opMode;
00049 unsigned int opAddr;
00050 SystemClockOffset eraseWriteDelayTime;
00051 SystemClockOffset eraseDelayTime;
00052 SystemClockOffset writeDelayTime;
00053 SystemClockOffset writeDoneTime;
00054
00055 public:
00056 enum {
00057 DEVMODE_NORMAL = 0,
00058 DEVMODE_EXTENDED
00059 };
00060
00061 enum {
00062 OPSTATE_READY,
00063 OPSTATE_ENABLED,
00064 OPSTATE_WRITE
00065 };
00066
00067 enum {
00068 CTRL_MODE_ERASEWRITE = 0,
00069 CTRL_READ = 1,
00070 CTRL_WRITE = 2,
00071 CTRL_ENABLE = 4,
00072 CTRL_IRQ = 8,
00073 CTRL_MODE_ERASE = 16,
00074 CTRL_MODE_WRITE = 32,
00075 CTRL_MODES = 48,
00076 };
00077
00078 HWEeprom(AvrDevice *core, HWIrqSystem *irqs, unsigned int size, unsigned int irqVec, int devMode = DEVMODE_NORMAL);
00079 virtual ~HWEeprom();
00080
00081 virtual unsigned int CpuCycle();
00082 void Reset();
00083 void ClearIrqFlag(unsigned int vector);
00084
00085 void WriteMem(unsigned char *, unsigned int offset, unsigned int size);
00086 void WriteAtAddress(unsigned int, unsigned char);
00087 unsigned char ReadFromAddress(unsigned int);
00088
00089 void SetEearl(unsigned char);
00090 void SetEearh(unsigned char);
00091 void SetEedr(unsigned char);
00092 void SetEecr(unsigned char);
00093
00094 unsigned char GetEearl() {return eear & 0xff; }
00095 unsigned char GetEearh() {return (eear >> 8) & 0xff; }
00096 unsigned char GetEecr() { return eecr; }
00097 unsigned char GetEedr() { return eedr; }
00098
00099 IOReg<HWEeprom>
00100 eearh_reg,
00101 eearl_reg,
00102 eedr_reg,
00103 eecr_reg;
00104 };
00105
00106 #endif