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00026 #include "decoder.h"
00027 #include "hwstack.h"
00028 #include "flash.h"
00029 #include "hwwado.h"
00030 #include "hwsreg.h"
00031 #include "global.h"
00032 #include "avrerror.h"
00033 #include "ioregs.h"
00034
00035 static int n_bit_unsigned_to_signed(unsigned int val, int n );
00036
00037 static int get_add_carry( byte res, byte rd, byte rr, int b );
00038 static int get_add_overflow( byte res, byte rd, byte rr );
00039 static int get_sub_carry( byte res, byte rd, byte rr, int b );
00040 static int get_sub_overflow( byte res, byte rd, byte rr );
00041 static int get_compare_carry( byte res, byte rd, byte rr, int b );
00042 static int get_compare_overflow( byte res, byte rd, byte rr );
00043
00044 enum decoder_operand_masks {
00046 mask_Rd_2 = 0x0030,
00048 mask_Rd_3 = 0x0070,
00050 mask_Rd_4 = 0x00f0,
00052 mask_Rd_5 = 0x01f0,
00053
00055 mask_Rr_3 = 0x0007,
00057 mask_Rr_4 = 0x000f,
00059 mask_Rr_5 = 0x020f,
00060
00062 mask_K_8 = 0x0F0F,
00064 mask_K_6 = 0x00CF,
00065
00067 mask_k_7 = 0x03F8,
00069 mask_k_12 = 0x0FFF,
00071 mask_k_22 = 0x01F1,
00072
00074 mask_reg_bit = 0x0007,
00076 mask_sreg_bit = 0x0070,
00078 mask_q_displ = 0x2C07,
00079
00081 mask_A_5 = 0x00F8,
00083 mask_A_6 = 0x060F
00084 };
00085
00086 static int get_rd_2( word opcode );
00087 static int get_rd_3( word opcode );
00088 static int get_rd_4( word opcode );
00089 static int get_rd_5( word opcode );
00090 static int get_rr_3( word opcode );
00091 static int get_rr_4( word opcode );
00092 static int get_rr_5( word opcode );
00093 static byte get_K_8( word opcode );
00094 static byte get_K_6( word opcode );
00095 static int get_k_7( word opcode );
00096 static int get_k_12( word opcode );
00097 static int get_k_22( word opcode );
00098 static int get_reg_bit( word opcode );
00099 static int get_sreg_bit( word opcode );
00100 static int get_q( word opcode );
00101 static int get_A_5( word opcode );
00102 static int get_A_6( word opcode );
00103
00104 avr_op_ADC::avr_op_ADC(word opcode, AvrDevice *c):
00105 DecodedInstruction(c),
00106 R1(get_rd_5(opcode)),
00107 R2(get_rr_5(opcode)),
00108 status(c->status) {}
00109
00110 unsigned char avr_op_ADC::GetModifiedR() const {
00111 return R1;
00112 }
00113 int avr_op_ADC::operator()() {
00114 unsigned char rd = core->GetCoreReg(R1);
00115 unsigned char rr = core->GetCoreReg(R2);
00116 unsigned char res = rd + rr + status->C;
00117
00118 status->H = get_add_carry(res, rd, rr, 3);
00119 status->V = get_add_overflow(res, rd, rr);
00120 status->N = (res >> 7) & 0x1;
00121 status->S = status->N ^ status->V;
00122 status->Z = (res & 0xff) == 0;
00123 status->C = get_add_carry(res, rd, rr, 7);
00124
00125 core->SetCoreReg(R1, res);
00126
00127 return 1;
00128 }
00129
00130 avr_op_ADD::avr_op_ADD(word opcode, AvrDevice *c):
00131 DecodedInstruction(c),
00132 R1(get_rd_5(opcode)),
00133 R2(get_rr_5(opcode)),
00134 status(c->status) {}
00135
00136 unsigned char avr_op_ADD::GetModifiedR() const {
00137 return R1;
00138 }
00139 int avr_op_ADD::operator()() {
00140 unsigned char rd = core->GetCoreReg(R1);
00141 unsigned char rr = core->GetCoreReg(R2);
00142 unsigned char res = rd + rr;
00143
00144 status->H = get_add_carry(res, rd, rr, 3);
00145 status->V = get_add_overflow(res, rd, rr);
00146 status->N = (res >> 7) & 0x1;
00147 status->S = status->N ^ status->V;
00148 status->Z = (res & 0xff) == 0;
00149 status->C = get_add_carry(res, rd, rr, 7);
00150
00151 core->SetCoreReg(R1, res);
00152
00153 return 1;
00154 }
00155
00156 avr_op_ADIW::avr_op_ADIW(word opcode, AvrDevice *c):
00157 DecodedInstruction(c),
00158 Rl(get_rd_2(opcode)),
00159 Rh(get_rd_2(opcode) + 1),
00160 K(get_K_6(opcode)),
00161 status(c->status) {
00162 }
00163
00164 unsigned char avr_op_ADIW::GetModifiedR() const {
00165 return Rl;
00166 }
00167 unsigned char avr_op_ADIW::GetModifiedRHi() const {
00168 return Rh;
00169 }
00170 int avr_op_ADIW::operator()() {
00171 word rd = (core->GetCoreReg(Rh) << 8) + core->GetCoreReg(Rl);
00172 word res = rd + K;
00173 unsigned char rdh = core->GetCoreReg(Rh);
00174
00175
00176 status->V = ~(rdh >> 7 & 0x1) & (res >> 15 & 0x1);
00177 status->N = (res >> 15) & 0x1;
00178 status->S = status->N ^ status->V;
00179 status->Z = (res & 0xffff) == 0;
00180 status->C = ~(res >> 15 & 0x1) & (rdh >> 7 & 0x1);
00181
00182 core->SetCoreReg(Rl, res & 0xff);
00183 core->SetCoreReg(Rh, res >> 8);
00184
00185 return 2;
00186 }
00187
00188 avr_op_AND::avr_op_AND(word opcode, AvrDevice *c):
00189 DecodedInstruction(c),
00190 R1(get_rd_5(opcode)),
00191 R2(get_rr_5(opcode)),
00192 status(c->status) {}
00193
00194 int avr_op_AND::operator()() {
00195 unsigned char res = core->GetCoreReg(R1) & core->GetCoreReg(R2);
00196
00197 status->V = 0;
00198 status->N = (res >> 7) & 0x1;
00199 status->S = status->N ^ status->V;
00200 status->Z = (res & 0xff) == 0;
00201
00202 core->SetCoreReg(R1, res);
00203
00204 return 1;
00205 }
00206
00207 avr_op_ANDI::avr_op_ANDI(word opcode, AvrDevice *c):
00208 DecodedInstruction(c),
00209 R1(get_rd_4(opcode)),
00210 status(c->status),
00211 K(get_K_8(opcode)) {}
00212
00213 int avr_op_ANDI::operator()() {
00214 unsigned char rd = core->GetCoreReg(R1);
00215 unsigned char res = rd & K;
00216
00217 status->V = 0;
00218 status->N = (res >> 7) & 0x1;
00219 status->S = status->N ^ status->V;
00220 status->Z = (res & 0xff) == 0;
00221
00222 core->SetCoreReg(R1, res);
00223
00224 return 1;
00225 }
00226
00227 avr_op_ASR::avr_op_ASR(word opcode, AvrDevice *c):
00228 DecodedInstruction(c),
00229 R1(get_rd_5(opcode)),
00230 status(c->status) {}
00231
00232 int avr_op_ASR::operator()() {
00233 unsigned char rd = core->GetCoreReg(R1);
00234 unsigned char res = (rd >> 1) + (rd & 0x80);
00235
00236 status->N = (res >> 7) & 0x1;
00237 status->C = rd & 0x1;
00238 status->V = status->N ^ status->C;
00239 status->S = status->N ^ status->V;
00240 status->Z = (res & 0xff) == 0;
00241
00242 core->SetCoreReg(R1, res);
00243
00244 return 1;
00245 }
00246
00247
00248 avr_op_BCLR::avr_op_BCLR(word opcode, AvrDevice *c):
00249 DecodedInstruction(c),
00250 status(c->status),
00251 Kbit(get_sreg_bit(opcode)) {}
00252
00253 int avr_op_BCLR::operator()() {
00254 *status = (*status) & ~(1 << Kbit);
00255
00256 return 1;
00257 }
00258
00259 avr_op_BLD::avr_op_BLD(word opcode, AvrDevice *c):
00260 DecodedInstruction(c),
00261 R1(get_rd_5(opcode)),
00262 Kbit(get_reg_bit(opcode)),
00263 status(c->status) {}
00264
00265 int avr_op_BLD::operator()() {
00266 unsigned char rd = core->GetCoreReg(R1);
00267 int T = status->T;
00268 unsigned char res;
00269
00270 if(T == 0)
00271 res = rd & ~(1 << Kbit);
00272 else
00273 res = rd | (1 << Kbit);
00274
00275 core->SetCoreReg(R1, res);
00276
00277 return 1;
00278 }
00279
00280 avr_op_BRBC::avr_op_BRBC(word opcode, AvrDevice *c):
00281 DecodedInstruction(c),
00282 status(c->status),
00283 bitmask(1 << get_reg_bit(opcode)),
00284 offset(n_bit_unsigned_to_signed(get_k_7(opcode), 7)) {}
00285
00286 int avr_op_BRBC::operator()() {
00287 int clks;
00288
00289 if((bitmask & (*(status))) == 0) {
00290 core->DebugOnJump();
00291 core->PC += offset;
00292 clks = 2;
00293 } else {
00294 clks = 1;
00295 }
00296
00297 return clks;
00298 }
00299
00300 avr_op_BRBS::avr_op_BRBS(word opcode, AvrDevice *c):
00301 DecodedInstruction(c),
00302 status(c->status),
00303 bitmask(1 << get_reg_bit(opcode)),
00304 offset(n_bit_unsigned_to_signed(get_k_7(opcode), 7)) {}
00305
00306 int avr_op_BRBS::operator()() {
00307 int clks;
00308
00309 if((bitmask & (*(status))) != 0) {
00310 core->DebugOnJump();
00311 core->PC += offset;
00312 clks = 2;
00313 } else {
00314 clks = 1;
00315 }
00316
00317 return clks;
00318 }
00319
00320 avr_op_BSET::avr_op_BSET(word opcode, AvrDevice *c):
00321 DecodedInstruction(c),
00322 status(c->status),
00323 Kbit(get_sreg_bit(opcode)) {}
00324
00325 int avr_op_BSET::operator()() {
00326 bool interruptsWereEnabled = status->I;
00327 *(status) = *(status) | 1 << Kbit;
00328
00329
00330
00331 if(!interruptsWereEnabled && status->I)
00332 core->instructionSEIJustEnabledInterrupts = true;
00333 return 1;
00334 }
00335
00336 avr_op_BST::avr_op_BST(word opcode, AvrDevice *c):
00337 DecodedInstruction(c),
00338 R1(get_rd_5(opcode)),
00339 status(c->status),
00340 Kbit(get_reg_bit(opcode)) {}
00341
00342 int avr_op_BST::operator()() {
00343 status->T = ((core->GetCoreReg(R1) & (1 << Kbit)) != 0);
00344
00345 return 1;
00346 }
00347
00348 avr_op_CALL::avr_op_CALL(word opcode, AvrDevice *c):
00349 DecodedInstruction(c, true),
00350 KH(get_k_22(opcode)) {}
00351
00352 int avr_op_CALL::operator()()
00353 {
00354 word K_lsb = core->Flash->ReadMemWord((core->PC + 1) * 2);
00355 int k = (KH << 16) + K_lsb;
00356 int clkadd = core->flagXMega ? 1 : 2;
00357
00358 core->stack->m_ThreadList.OnCall();
00359 core->stack->PushAddr(core->PC + 2);
00360 core->DebugOnJump();
00361 core->PC = k - 1;
00362
00363 return core->PC_size + clkadd;
00364 }
00365
00366 avr_op_CBI::avr_op_CBI(word opcode, AvrDevice *c):
00367 DecodedInstruction(c),
00368 ioreg(get_A_5(opcode)),
00369 Kbit(get_reg_bit(opcode)) {}
00370
00371 int avr_op_CBI::operator()() {
00372 int clks = (core->flagXMega || core->flagTiny10) ? 1 : 2;
00373
00374 core->SetIORegBit(ioreg, Kbit, false);
00375
00376 return clks;
00377 }
00378
00379 avr_op_COM::avr_op_COM(word opcode, AvrDevice *c):
00380 DecodedInstruction(c),
00381 R1(get_rd_5(opcode)),
00382 status(c->status) {}
00383
00384 int avr_op_COM::operator()() {
00385 byte rd = core->GetCoreReg(R1);
00386 byte res = 0xff - rd;
00387
00388 status->N = (res >> 7) & 0x1;
00389 status->C = 1;
00390 status->V = 0;
00391 status->S = status->N ^ status->V;
00392 status->Z = (res & 0xff) == 0;
00393
00394 core->SetCoreReg(R1, res);
00395
00396 return 1;
00397 }
00398
00399 avr_op_CP::avr_op_CP(word opcode, AvrDevice *c):
00400 DecodedInstruction(c),
00401 R1(get_rd_5(opcode)),
00402 R2(get_rr_5(opcode)),
00403 status(c->status) {}
00404
00405 int avr_op_CP::operator()() {
00406 byte rd = core->GetCoreReg(R1);
00407 byte rr = core->GetCoreReg(R2);
00408 byte res = rd - rr;
00409
00410 status->H = get_compare_carry(res, rd, rr, 3);
00411 status->V = get_compare_overflow(res, rd, rr);
00412 status->N = (res >> 7) & 0x1;
00413 status->S = status->N ^ status->V;
00414 status->Z = (res & 0xff) == 0;
00415 status->C = get_compare_carry(res, rd, rr, 7);
00416
00417 return 1;
00418 }
00419
00420 avr_op_CPC::avr_op_CPC(word opcode, AvrDevice *c):
00421 DecodedInstruction(c),
00422 R1(get_rd_5(opcode)),
00423 R2(get_rr_5(opcode)),
00424 status(c->status) {}
00425
00426 int avr_op_CPC::operator()() {
00427 byte rd = core->GetCoreReg(R1);
00428 byte rr = core->GetCoreReg(R2);
00429 byte res = rd - rr - status->C;
00430
00431 status->H = get_compare_carry(res, rd, rr, 3);
00432 status->V = get_compare_overflow(res, rd, rr);
00433 status->N = (res >> 7) & 0x1;
00434 status->S = status->N ^ status->V;
00435 status->C = get_compare_carry(res, rd, rr, 7);
00436
00437
00438 bool Z = (res & 0xff) == 0;
00439 bool prev_Z = status->Z;
00440 status->Z = Z && prev_Z;
00441
00442 return 1;
00443 }
00444
00445
00446 avr_op_CPI::avr_op_CPI(word opcode, AvrDevice *c):
00447 DecodedInstruction(c),
00448 R1(get_rd_4(opcode)),
00449 status(c->status),
00450 K(get_K_8(opcode)) {}
00451
00452 int avr_op_CPI::operator()() {
00453 byte rd = core->GetCoreReg(R1);
00454 byte res = rd - K;
00455
00456 status->H = get_compare_carry(res, rd, K, 3);
00457 status->V = get_compare_overflow(res, rd, K);
00458 status->N = (res >> 7) & 0x1;
00459 status->S = status->N ^ status->V;
00460 status->Z = (res & 0xff) == 0;
00461 status->C = get_compare_carry(res, rd, K, 7);
00462
00463 return 1;
00464 }
00465
00466 avr_op_CPSE::avr_op_CPSE(word opcode, AvrDevice *c):
00467 DecodedInstruction(c),
00468 R1(get_rd_5(opcode)),
00469 R2(get_rr_5(opcode)),
00470 status(c->status) {}
00471
00472 int avr_op_CPSE::operator()() {
00473 int skip;
00474 byte rd = core->GetCoreReg(R1);
00475 byte rr = core->GetCoreReg(R2);
00476 int clks;
00477
00478 if(core->Flash->DecodedMem[core->PC + 1]->IsInstruction2Words())
00479 skip = 3;
00480 else
00481 skip = 2;
00482
00483 if(rd == rr) {
00484 core->DebugOnJump();
00485 core->PC += skip - 1;
00486 clks = skip;
00487 } else
00488 clks = 1;
00489
00490 return clks;
00491 }
00492
00493 avr_op_DEC::avr_op_DEC(word opcode, AvrDevice *c):
00494 DecodedInstruction(c),
00495 R1(get_rd_5(opcode)),
00496 status(c->status) {}
00497
00498 int avr_op_DEC::operator()() {
00499 byte res = core->GetCoreReg(R1) - 1;
00500
00501 status->N = (res >> 7) & 0x1;
00502 status->V = res == 0x7f;
00503 status->S = status->N ^ status->V;
00504 status->Z = (res & 0xff) == 0;
00505
00506 core->SetCoreReg(R1, res);
00507
00508 return 1;
00509 }
00510
00511 avr_op_EICALL::avr_op_EICALL(word opcode, AvrDevice *c):
00512 DecodedInstruction(c) {}
00513
00514 int avr_op_EICALL::operator()() {
00515 unsigned new_PC = core->GetRegZ() + (core->eind->GetRegVal() << 16);
00516
00517 core->stack->m_ThreadList.OnCall();
00518 core->stack->PushAddr(core->PC + 1);
00519
00520 core->DebugOnJump();
00521 core->PC = new_PC;
00522
00523 return core->flagXMega ? 3 : 4;
00524 }
00525
00526 avr_op_EIJMP::avr_op_EIJMP(word opcode, AvrDevice *c):
00527 DecodedInstruction(c) {}
00528
00529 int avr_op_EIJMP::operator()() {
00530 core->DebugOnJump();
00531 core->PC = (core->eind->GetRegVal() << 16) + core->GetRegZ();
00532
00533 return 2;
00534 }
00535
00536 avr_op_ELPM_Z::avr_op_ELPM_Z(word opcode, AvrDevice *c):
00537 DecodedInstruction(c),
00538 R1(get_rd_5(opcode)) {}
00539
00540 int avr_op_ELPM_Z::operator()() {
00541 unsigned int Z;
00542 unsigned char rampz = 0;
00543
00544 if(core->rampz != NULL)
00545 rampz = core->rampz->GetRegVal();
00546 Z = (rampz << 16) + core->GetRegZ();
00547
00548 core->SetCoreReg(R1, core->Flash->ReadMem(Z ^ 0x1));
00549
00550 return 3;
00551 }
00552
00553 avr_op_ELPM_Z_incr::avr_op_ELPM_Z_incr(word opcode, AvrDevice *c):
00554 DecodedInstruction(c),
00555 R1(get_rd_5(opcode)) {}
00556
00557 int avr_op_ELPM_Z_incr::operator()() {
00558 unsigned int Z;
00559 unsigned char rampz = 0;
00560
00561 if(core->rampz != NULL)
00562 rampz = core->rampz->GetRegVal();
00563 Z = (rampz << 16) + core->GetRegZ();
00564
00565 core->SetCoreReg(R1, core->Flash->ReadMem(Z ^ 0x1));
00566
00567
00568 Z++;
00569 if(core->rampz != NULL)
00570 core->rampz->SetRegVal(Z >> 16);
00571 core->SetCoreReg(30, Z & 0xff);
00572 core->SetCoreReg(31, (Z >> 8) & 0xff);
00573
00574 return 3;
00575 }
00576
00577 avr_op_ELPM::avr_op_ELPM(word opcode, AvrDevice *c):
00578 DecodedInstruction(c) {}
00579
00580 int avr_op_ELPM::operator()() {
00581 unsigned char rampz = 0;
00582
00583 if(core->rampz != NULL)
00584 rampz = core->rampz->GetRegVal();
00585 unsigned Z = (rampz << 16) + core->GetRegZ();
00586
00587 core->SetCoreReg(0, core->Flash->ReadMem(Z ^ 0x1));
00588
00589 return 3;
00590 }
00591
00592 avr_op_EOR::avr_op_EOR(word opcode, AvrDevice *c):
00593 DecodedInstruction(c),
00594 R1(get_rd_5(opcode)),
00595 R2(get_rr_5(opcode)),
00596 status(c->status) {}
00597
00598 int avr_op_EOR::operator()() {
00599 byte rd = core->GetCoreReg(R1);
00600 byte rr = core->GetCoreReg(R2);
00601 byte res = rd ^ rr;
00602
00603 status->V = 0;
00604 status->N = (res >> 7) & 0x1;
00605 status->S = status->N ^ status->V;
00606 status->Z = (res & 0xff) == 0;
00607
00608 core->SetCoreReg(R1, res);
00609
00610 return 1;
00611 }
00612
00613 avr_op_ESPM::avr_op_ESPM(word opcode, AvrDevice *c):
00614 DecodedInstruction(c) {}
00615
00616 int avr_op_ESPM::operator()() {
00617 unsigned char xaddr = 0;
00618 int cycles = 1;
00619 if(core->rampz != NULL)
00620 xaddr = core->rampz->GetRegVal();
00621 if(core->spmRegister != NULL) {
00622 unsigned int Z = core->GetRegZ();
00623 unsigned int D = core->GetCoreReg(0) + (core->GetCoreReg(1) << 8);
00624 cycles += core->spmRegister->SPM_action(D, xaddr, Z);
00625
00626 Z++;
00627 core->SetCoreReg(30, Z & 0xff);
00628 core->SetCoreReg(31, (Z >> 8) & 0xff);
00629 if(core->rampz != NULL)
00630 core->rampz->SetRegVal(Z >> 16);
00631 }
00632 return cycles;
00633 }
00634
00635 avr_op_FMUL::avr_op_FMUL(word opcode, AvrDevice *c):
00636 DecodedInstruction(c),
00637 Rd(get_rd_3(opcode)),
00638 Rr(get_rr_3(opcode)),
00639 status(c->status) {}
00640
00641 int avr_op_FMUL::operator()() {
00642 byte rd = core->GetCoreReg(Rd);
00643 byte rr = core->GetCoreReg(Rr);
00644
00645 word resp = rd * rr;
00646 word res = resp << 1;
00647
00648 status->Z = (res & 0xffff) == 0;
00649 status->C= (resp >> 15) & 0x1;
00650
00651
00652 core->SetCoreReg(0, res & 0xff);
00653 core->SetCoreReg(1, (res >> 8) & 0xff);
00654
00655 return 2;
00656 }
00657
00658
00659 avr_op_FMULS::avr_op_FMULS(word opcode, AvrDevice *c):
00660 DecodedInstruction(c),
00661 Rd(get_rd_3(opcode)),
00662 Rr(get_rr_3(opcode)),
00663 status(c->status) {}
00664
00665 int avr_op_FMULS::operator()() {
00666 sbyte rd = core->GetCoreReg(Rd);
00667 sbyte rr = core->GetCoreReg(Rr);
00668
00669 word resp = rd * rr;
00670 word res = resp << 1;
00671
00672 status->Z = (res & 0xffff) == 0;
00673 status->C = (resp >> 15) & 0x1;
00674
00675
00676 core->SetCoreReg(0, res & 0xff);
00677 core->SetCoreReg(1, (res >> 8) & 0xff);
00678
00679 return 2;
00680 }
00681
00682
00683 avr_op_FMULSU::avr_op_FMULSU(word opcode, AvrDevice *c):
00684 DecodedInstruction(c),
00685 Rd(get_rd_3(opcode)),
00686 Rr(get_rr_3(opcode)),
00687 status(c->status) {}
00688
00689 int avr_op_FMULSU::operator()() {
00690 sbyte rd = core->GetCoreReg(Rd);
00691 byte rr = core->GetCoreReg(Rr);
00692
00693 word resp = rd * rr;
00694 word res = resp << 1;
00695
00696 status->Z = (res & 0xffff) == 0;
00697 status->C = (resp >> 15) & 0x1;
00698
00699
00700 core->SetCoreReg(0, res & 0xff);
00701 core->SetCoreReg(1, (res >> 8) & 0xff);
00702 return 2;
00703 }
00704
00705 avr_op_ICALL::avr_op_ICALL(word opcode, AvrDevice *c):
00706 DecodedInstruction(c) {}
00707
00708 int avr_op_ICALL::operator()() {
00709 unsigned int pc = core->PC;
00710
00711 unsigned int new_pc = core->GetRegZ();
00712
00713 core->stack->m_ThreadList.OnCall();
00714 core->stack->PushAddr(pc + 1);
00715
00716 core->DebugOnJump();
00717 core->PC = new_pc - 1;
00718
00719 return core->PC_size + (core->flagXMega ? 0 : 1);
00720 }
00721
00722 avr_op_IJMP::avr_op_IJMP(word opcode, AvrDevice *c):
00723 DecodedInstruction(c) {}
00724
00725 int avr_op_IJMP::operator()() {
00726 int new_pc = core->GetRegZ();
00727
00728 core->DebugOnJump();
00729 core->PC = new_pc - 1;
00730
00731 return 2;
00732 }
00733
00734 avr_op_IN::avr_op_IN(word opcode, AvrDevice *c):
00735 DecodedInstruction(c),
00736 R1(get_rd_5(opcode)),
00737 ioreg(get_A_6(opcode)) {}
00738
00739 int avr_op_IN::operator()() {
00740 core->SetCoreReg(R1, core->GetIOReg(ioreg));
00741
00742 return 1;
00743 }
00744
00745 avr_op_INC::avr_op_INC(word opcode, AvrDevice *c):
00746 DecodedInstruction(c),
00747 R1(get_rd_5(opcode)),
00748 status(c->status) {}
00749
00750 int avr_op_INC::operator()() {
00751 byte rd = core->GetCoreReg(R1);
00752 byte res = rd + 1;
00753
00754 status->N = (res >> 7) & 0x1;
00755 status->V = rd == 0x7f;
00756 status->S = status->N ^ status->V;
00757 status->Z = (res & 0xff) == 0;
00758
00759 core->SetCoreReg(R1, res);
00760
00761 return 1;
00762 }
00763
00764 avr_op_JMP::avr_op_JMP(word opcode, AvrDevice *c):
00765 DecodedInstruction(c, true),
00766 K(get_k_22(opcode)) {}
00767
00768 int avr_op_JMP::operator()() {
00769 word K_lsb = core->Flash->ReadMemWord((core->PC + 1) * 2);
00770 core->DebugOnJump();
00771 core->PC = (K << 16) + K_lsb - 1;
00772 return 3;
00773 }
00774
00775 avr_op_LDD_Y::avr_op_LDD_Y(word opcode, AvrDevice *c):
00776 DecodedInstruction(c),
00777 Rd(get_rd_5(opcode)),
00778 K(get_q(opcode)) {}
00779
00780 int avr_op_LDD_Y::operator()() {
00781
00782 word Y = core->GetRegY();
00783
00784 core->SetCoreReg(Rd, core->GetRWMem(Y + K));
00785
00786 return ((core->flagXMega || core->flagTiny10) && K == 0) ? 1 : 2;
00787 }
00788
00789 avr_op_LDD_Z::avr_op_LDD_Z(word opcode, AvrDevice *c):
00790 DecodedInstruction(c),
00791 Rd(get_rd_5(opcode)),
00792 K(get_q(opcode)) {}
00793
00794 int avr_op_LDD_Z::operator()() {
00795
00796 word Z = core->GetRegZ();
00797
00798 core->SetCoreReg(Rd, core->GetRWMem(Z + K));
00799
00800 return ((core->flagXMega || core->flagTiny10) && K == 0) ? 1 : 2;
00801 }
00802
00803 avr_op_LDI::avr_op_LDI(word opcode, AvrDevice *c):
00804 DecodedInstruction(c),
00805 R1(get_rd_4(opcode)),
00806 K(get_K_8(opcode)) {}
00807
00808 unsigned char avr_op_LDI::GetModifiedR() const {
00809 return R1;
00810 }
00811 int avr_op_LDI::operator()() {
00812 core->SetCoreReg(R1, K);
00813
00814 return 1;
00815 }
00816
00817 avr_op_LDS::avr_op_LDS(word opcode, AvrDevice *c):
00818 DecodedInstruction(c, true),
00819 R1(get_rd_5(opcode)) {}
00820
00821 int avr_op_LDS::operator()() {
00822
00823 word offset = core->Flash->ReadMemWord((core->PC + 1) * 2);
00824
00825 core->SetCoreReg(R1, core->GetRWMem(offset));
00826 core->PC++;
00827
00828 return 2;
00829 }
00830
00831 avr_op_LD_X::avr_op_LD_X(word opcode, AvrDevice *c):
00832 DecodedInstruction(c),
00833 Rd(get_rd_5(opcode)) {}
00834
00835 int avr_op_LD_X::operator()() {
00836
00837 word X = core->GetRegX();
00838
00839 core->SetCoreReg(Rd, core->GetRWMem(X));
00840
00841 return (core->flagXMega || core->flagTiny10) ? 1 : 2;
00842 }
00843
00844 avr_op_LD_X_decr::avr_op_LD_X_decr(word opcode, AvrDevice *c):
00845 DecodedInstruction(c),
00846 Rd(get_rd_5(opcode)) {}
00847
00848 int avr_op_LD_X_decr::operator()() {
00849
00850 word X = core->GetRegX();
00851 if (Rd == 26 || Rd == 27)
00852 avr_error( "Result of operation is undefined" );
00853
00854
00855 X--;
00856 core->SetCoreReg(Rd, core->GetRWMem(X));
00857 core->SetCoreReg(26, X & 0xff);
00858 core->SetCoreReg(27, (X >> 8) & 0xff);
00859
00860 return core->flagTiny10 ? 3 : 2;
00861 }
00862
00863 avr_op_LD_X_incr::avr_op_LD_X_incr(word opcode, AvrDevice *c):
00864 DecodedInstruction(c),
00865 Rd(get_rd_5(opcode)) {}
00866
00867 int avr_op_LD_X_incr::operator()() {
00868
00869 word X = core->GetRegX();
00870 if (Rd == 26 || Rd == 27)
00871 avr_error( "Result of operation is undefined" );
00872
00873
00874 core->SetCoreReg(Rd, core->GetRWMem(X));
00875 X++;
00876 core->SetCoreReg(26, X & 0xff);
00877 core->SetCoreReg(27, (X >> 8) & 0xff);
00878
00879 return core->flagXMega ? 1 : 2;
00880 }
00881
00882 avr_op_LD_Y_decr::avr_op_LD_Y_decr(word opcode, AvrDevice *c):
00883 DecodedInstruction(c),
00884 Rd(get_rd_5(opcode)) {}
00885
00886 int avr_op_LD_Y_decr::operator()() {
00887
00888 word Y = core->GetRegY();
00889 if (Rd == 28 || Rd == 29)
00890 avr_error( "Result of operation is undefined" );
00891
00892
00893 Y--;
00894 core->SetCoreReg(Rd, core->GetRWMem(Y));
00895 core->SetCoreReg(28, Y & 0xff);
00896 core->SetCoreReg(29, (Y >> 8) & 0xff);
00897
00898 return core->flagTiny10 ? 3 : 2;
00899 }
00900
00901 avr_op_LD_Y_incr::avr_op_LD_Y_incr(word opcode, AvrDevice *c):
00902 DecodedInstruction(c),
00903 Rd(get_rd_5(opcode)) {}
00904
00905 int avr_op_LD_Y_incr::operator()() {
00906
00907 word Y = core->GetRegY();
00908 if (Rd == 28 || Rd == 29)
00909 avr_error( "Result of operation is undefined" );
00910
00911
00912 core->SetCoreReg(Rd, core->GetRWMem(Y));
00913 Y++;
00914 core->SetCoreReg(28, Y & 0xff);
00915 core->SetCoreReg(29, (Y >> 8) & 0xff);
00916
00917 return core->flagXMega ? 1 : 2;
00918 }
00919
00920 avr_op_LD_Z_incr::avr_op_LD_Z_incr(word opcode, AvrDevice *c):
00921 DecodedInstruction(c),
00922 Rd(get_rd_5(opcode)) {}
00923
00924 int avr_op_LD_Z_incr::operator()() {
00925
00926 word Z = core->GetRegZ();
00927 if (Rd == 30 || Rd == 31)
00928 avr_error( "Result of operation is undefined" );
00929
00930
00931 core->SetCoreReg(Rd, core->GetRWMem(Z));
00932 Z++;
00933 core->SetCoreReg(30, Z & 0xff);
00934 core->SetCoreReg(31, (Z >> 8) & 0xff);
00935
00936 return core->flagXMega ? 1 : 2;
00937 }
00938
00939 avr_op_LD_Z_decr::avr_op_LD_Z_decr(word opcode, AvrDevice *c):
00940 DecodedInstruction(c),
00941 Rd(get_rd_5(opcode)) {}
00942
00943 int avr_op_LD_Z_decr::operator()() {
00944
00945 word Z = core->GetRegZ();
00946 if (Rd == 30 || Rd == 31)
00947 avr_error( "Result of operation is undefined" );
00948
00949
00950 Z--;
00951 core->SetCoreReg(Rd, core->GetRWMem(Z));
00952 core->SetCoreReg(30, Z & 0xff);
00953 core->SetCoreReg(31, (Z >> 8) & 0xff);
00954
00955 return core->flagTiny10 ? 3 : 2;
00956 }
00957
00958 avr_op_LPM_Z::avr_op_LPM_Z(word opcode, AvrDevice *c):
00959 DecodedInstruction(c),
00960 Rd(get_rd_5(opcode)) {}
00961
00962 int avr_op_LPM_Z::operator()() {
00963
00964 word Z = core->GetRegZ();
00965
00966 Z ^= 0x0001;
00967 core->SetCoreReg(Rd , core->Flash->ReadMem(Z));
00968
00969 return 3;
00970 }
00971
00972 avr_op_LPM::avr_op_LPM(word opcode, AvrDevice *c):
00973 DecodedInstruction(c) {}
00974
00975 int avr_op_LPM::operator()() {
00976
00977 word Z = core->GetRegZ();
00978
00979 Z ^= 0x0001;
00980 core->SetCoreReg(0 , core->Flash->ReadMem(Z));
00981
00982 return 3;
00983 }
00984
00985 avr_op_LPM_Z_incr::avr_op_LPM_Z_incr(word opcode, AvrDevice *c):
00986 DecodedInstruction(c),
00987 Rd(get_rd_5(opcode)) {}
00988
00989 int avr_op_LPM_Z_incr::operator()() {
00990
00991 word Z = core->GetRegZ();
00992
00993 core->SetCoreReg(Rd , core->Flash->ReadMem(Z ^ 0x0001));
00994
00995 Z++;
00996 core->SetCoreReg(30, Z & 0xff);
00997 core->SetCoreReg(31, (Z >> 8) & 0xff);
00998
00999 return 3;
01000 }
01001
01002 avr_op_LSR::avr_op_LSR(word opcode, AvrDevice *c):
01003 DecodedInstruction(c),
01004 Rd(get_rd_5(opcode)),
01005 status(c->status) {}
01006
01007 int avr_op_LSR::operator()() {
01008 byte rd = core->GetCoreReg(Rd);
01009
01010 byte res = (rd >> 1) & 0x7f;
01011
01012 status->C = rd & 0x1;
01013 status->N = 0;
01014 status->V = status->N ^ status->C;
01015 status->S = status->N ^ status->V;
01016 status->Z = (res & 0xff) == 0;
01017
01018 core->SetCoreReg(Rd, res);
01019
01020 return 1;
01021 }
01022
01023 avr_op_MOV::avr_op_MOV(word opcode, AvrDevice *c):
01024 DecodedInstruction(c),
01025 R1(get_rd_5(opcode)),
01026 R2(get_rr_5(opcode)) {}
01027
01028 int avr_op_MOV::operator()() {
01029 core->SetCoreReg(R1, core->GetCoreReg(R2));
01030 return 1;
01031 }
01032
01033 avr_op_MOVW::avr_op_MOVW(word opcode, AvrDevice *c):
01034 DecodedInstruction(c),
01035 Rd((get_rd_4(opcode) - 16) << 1),
01036 Rs((get_rr_4(opcode) - 16) << 1) {}
01037
01038 int avr_op_MOVW::operator()() {
01039 core->SetCoreReg(Rd, core->GetCoreReg(Rs));
01040 core->SetCoreReg(Rd + 1, core->GetCoreReg(Rs + 1));
01041
01042 return 1;
01043 }
01044
01045 avr_op_MUL::avr_op_MUL(word opcode, AvrDevice *c):
01046 DecodedInstruction(c),
01047 Rd(get_rd_5(opcode)),
01048 Rr(get_rr_5(opcode)),
01049 status(c->status) {}
01050
01051 int avr_op_MUL::operator()() {
01052 byte rd = core->GetCoreReg(Rd);
01053 byte rr = core->GetCoreReg(Rr);
01054
01055 word res = rd * rr;
01056
01057 status->Z = (res & 0xffff) == 0;
01058 status->C = (res >> 15) & 0x1;
01059
01060
01061 core->SetCoreReg(0, res & 0xff);
01062 core->SetCoreReg(1, (res >> 8) & 0xff);
01063
01064 return 2;
01065 }
01066
01067 avr_op_MULS::avr_op_MULS(word opcode, AvrDevice *c):
01068 DecodedInstruction(c),
01069 Rd(get_rd_4(opcode)),
01070 Rr(get_rr_4(opcode)),
01071 status(c->status) {}
01072
01073 int avr_op_MULS::operator()() {
01074 sbyte rd = (sbyte)core->GetCoreReg(Rd);
01075 sbyte rr = (sbyte)core->GetCoreReg(Rr);
01076
01077 sword res = rd * rr;
01078
01079 status->Z = (res & 0xffff) == 0;
01080 status->C = (res >> 15) & 0x1;
01081
01082
01083 core->SetCoreReg(0, res & 0xff);
01084 core->SetCoreReg(1, (res >> 8) & 0xff);
01085
01086 return 2;
01087 }
01088
01089 avr_op_MULSU::avr_op_MULSU(word opcode, AvrDevice *c):
01090 DecodedInstruction(c),
01091 Rd(get_rd_3(opcode)),
01092 Rr(get_rr_3(opcode)),
01093 status(c->status) {}
01094
01095 int avr_op_MULSU::operator()() {
01096 sbyte rd = (sbyte)core->GetCoreReg(Rd);
01097 byte rr = core->GetCoreReg(Rr);
01098
01099 sword res = rd * rr;
01100
01101 status->Z = (res & 0xffff) == 0;
01102 status->C = (res >> 15) & 0x1;
01103
01104
01105
01106 core->SetCoreReg(0, res & 0xff);
01107 core->SetCoreReg(1, (res >> 8) & 0xff);
01108
01109 return 2;
01110 }
01111
01112 avr_op_NEG::avr_op_NEG(word opcode, AvrDevice *c):
01113 DecodedInstruction(c),
01114 Rd(get_rd_5(opcode)),
01115 status(c->status) {}
01116
01117 int avr_op_NEG::operator()() {
01118 byte rd = core->GetCoreReg(Rd);
01119 byte res = (0x0 - rd) & 0xff;
01120
01121 status->H = ((res >> 3) | (rd >> 3)) & 0x1;
01122 status->V = res == 0x80;
01123 status->N = (res >> 7) & 0x1;
01124 status->S = status->N ^ status->V;
01125 status->Z = res == 0x0;
01126 status->C = res != 0x0;
01127
01128 core->SetCoreReg(Rd, res);
01129
01130 return 1;
01131 }
01132
01133 avr_op_NOP::avr_op_NOP(word opcode, AvrDevice *c):
01134 DecodedInstruction(c) {}
01135
01136 int avr_op_NOP::operator()() {
01137 return 1;
01138 }
01139
01140 avr_op_OR::avr_op_OR(word opcode, AvrDevice *c):
01141 DecodedInstruction(c),
01142 Rd(get_rd_5(opcode)),
01143 Rr(get_rr_5(opcode)),
01144 status(c->status) {}
01145
01146 int avr_op_OR::operator()() {
01147 byte res = core->GetCoreReg(Rd) | core->GetCoreReg(Rr);
01148
01149 status->V = 0;
01150 status->N = (res >> 7) & 0x1;
01151 status->S = status->N ^ status->V;
01152 status->Z = res == 0x0;
01153
01154 core->SetCoreReg(Rd, res);
01155
01156 return 1;
01157 }
01158
01159 avr_op_ORI::avr_op_ORI(word opcode, AvrDevice *c):
01160 DecodedInstruction(c),
01161 R1(get_rd_4(opcode)),
01162 status(c->status),
01163 K(get_K_8(opcode)) {}
01164
01165 int avr_op_ORI::operator()() {
01166 byte res = core->GetCoreReg(R1) | K;
01167
01168 status->V = 0;
01169 status->N = (res >> 7) & 0x1;
01170 status->S = status->N ^ status->V;
01171 status->Z = res == 0x0;
01172
01173 core->SetCoreReg(R1, res);
01174
01175 return 1;
01176 }
01177
01178 avr_op_OUT::avr_op_OUT(word opcode, AvrDevice *c):
01179 DecodedInstruction(c),
01180 ioreg(get_A_6(opcode)),
01181 R1(get_rd_5(opcode)) {}
01182
01183 int avr_op_OUT::operator()() {
01184 core->SetIOReg(ioreg, core->GetCoreReg(R1));
01185
01186 return 1;
01187 }
01188
01189 avr_op_POP::avr_op_POP(word opcode, AvrDevice *c):
01190 DecodedInstruction(c),
01191 R1(get_rd_5(opcode)) {}
01192
01193 int avr_op_POP::operator()() {
01194 core->SetCoreReg(R1, core->stack->Pop());
01195
01196 return 2;
01197 }
01198
01199 avr_op_PUSH::avr_op_PUSH(word opcode, AvrDevice *c):
01200 DecodedInstruction(c),
01201 R1(get_rd_5(opcode)) {}
01202
01203 int avr_op_PUSH::operator()() {
01204 core->stack->Push(core->GetCoreReg(R1));
01205
01206 return core->flagXMega ? 1 : 2;
01207 }
01208
01209 avr_op_RCALL::avr_op_RCALL(word opcode, AvrDevice *c):
01210 DecodedInstruction(c),
01211 K(n_bit_unsigned_to_signed(get_k_12(opcode), 12)) {}
01212
01213 int avr_op_RCALL::operator()() {
01214 core->stack->PushAddr(core->PC + 1);
01215 core->stack->m_ThreadList.OnCall();
01216 core->DebugOnJump();
01217 core->PC += K;
01218 core->PC &= (core->Flash->GetSize() - 1) >> 1;
01219
01220 if(core->flagTiny10)
01221 return 4;
01222 return core->PC_size + (core->flagXMega ? 0 : 1);
01223
01224 }
01225
01226 avr_op_RET::avr_op_RET(word opcode, AvrDevice *c):
01227 DecodedInstruction(c) {}
01228
01229 int avr_op_RET::operator()() {
01230 core->PC = core->stack->PopAddr() - 1;
01231
01232 return core->PC_size + 2;
01233 }
01234
01235 avr_op_RETI::avr_op_RETI(word opcode, AvrDevice *c):
01236 DecodedInstruction(c),
01237 status(c->status) {}
01238
01239 int avr_op_RETI::operator()() {
01240 core->PC = core->stack->PopAddr() - 1;
01241 status->I = 1;
01242
01243 return core->PC_size + 2;
01244 }
01245
01246 avr_op_RJMP::avr_op_RJMP(word opcode, AvrDevice *c):
01247 DecodedInstruction(c),
01248 K(n_bit_unsigned_to_signed(get_k_12(opcode), 12)) {}
01249
01250 int avr_op_RJMP::operator()() {
01251 core->DebugOnJump();
01252 core->PC += K;
01253 core->PC &= (core->Flash->GetSize() - 1) >> 1;
01254
01255 return 2;
01256 }
01257
01258 avr_op_ROR::avr_op_ROR(word opcode, AvrDevice *c):
01259 DecodedInstruction(c),
01260 R1(get_rd_5(opcode)),
01261 status(c->status) {}
01262
01263 int avr_op_ROR::operator()() {
01264 byte rd = core->GetCoreReg(R1);
01265
01266 byte res = (rd >> 1) | ((status->C << 7) & 0x80);
01267
01268 status->C = rd & 0x1;
01269 status->N = (res >> 7) & 0x1;
01270 status->V = status->N ^ status->C;
01271 status->S = status->N ^ status->V;
01272 status->Z = res == 0;
01273
01274 core->SetCoreReg(R1, res);
01275
01276 return 1;
01277 }
01278
01279
01280 avr_op_SBC::avr_op_SBC(word opcode, AvrDevice *c):
01281 DecodedInstruction(c),
01282 R1(get_rd_5(opcode)),
01283 R2(get_rr_5(opcode)),
01284 status(c->status) {}
01285
01286 unsigned char avr_op_SBC::GetModifiedR() const {
01287 return R1;
01288 }
01289 int avr_op_SBC::operator()() {
01290 byte rd = core->GetCoreReg(R1);
01291 byte rr = core->GetCoreReg(R2);
01292
01293 byte res = rd - rr - status->C;
01294
01295 status->H = get_sub_carry(res, rd, rr, 3);
01296 status->V = get_sub_overflow(res, rd, rr);
01297 status->N = (res >> 7) & 0x1;
01298 status->S = status->N ^ status->V;
01299 status->C = get_sub_carry(res, rd, rr, 7);
01300
01301 if((res & 0xff) != 0)
01302 status->Z = 0;
01303
01304 core->SetCoreReg(R1, res);
01305
01306 return 1;
01307 }
01308
01309 avr_op_SBCI::avr_op_SBCI(word opcode, AvrDevice *c):
01310 DecodedInstruction(c),
01311 R1(get_rd_4(opcode)),
01312 status(c->status),
01313 K(get_K_8(opcode)) {}
01314
01315 unsigned char avr_op_SBCI::GetModifiedR() const {
01316 return R1;
01317 }
01318 int avr_op_SBCI::operator()() {
01319 byte rd = core->GetCoreReg(R1);
01320
01321 byte res = rd - K - status->C;
01322
01323 status->H = get_sub_carry(res, rd, K, 3);
01324 status->V = get_sub_overflow(res, rd, K);
01325 status->N = (res >> 7) & 0x1;
01326 status->S = status->N ^ status->V;
01327 status->C = get_sub_carry(res, rd, K, 7);
01328
01329 if((res & 0xff) != 0)
01330 status->Z = 0;
01331
01332 core->SetCoreReg(R1, res);
01333
01334 return 1;
01335 }
01336
01337 avr_op_SBI::avr_op_SBI(word opcode, AvrDevice *c):
01338 DecodedInstruction(c),
01339 ioreg(get_A_5(opcode)),
01340 Kbit(get_reg_bit(opcode)) {}
01341
01342 int avr_op_SBI::operator()() {
01343 int clks = (core->flagXMega || core->flagTiny10) ? 1 : 2;
01344
01345 core->SetIORegBit(ioreg, Kbit, true);
01346
01347 return clks;
01348 }
01349
01350 avr_op_SBIC::avr_op_SBIC(word opcode, AvrDevice *c):
01351 DecodedInstruction(c),
01352 ioreg(get_A_5(opcode)),
01353 Kbit(get_reg_bit(opcode)) {}
01354
01355 int avr_op_SBIC::operator()() {
01356 int skip, clks;
01357
01358 if(core->Flash->DecodedMem[core->PC + 1]->IsInstruction2Words())
01359 skip = 3;
01360 else
01361 skip = 2;
01362
01363 if((core->GetIOReg(ioreg) & (1 << Kbit)) == 0) {
01364 core->DebugOnJump();
01365 core->PC += skip - 1;
01366 clks = skip;
01367 } else
01368 clks = 1;
01369
01370 if(core->flagXMega)
01371 clks++;
01372
01373 return clks;
01374 }
01375
01376 avr_op_SBIS::avr_op_SBIS(word opcode, AvrDevice *c):
01377 DecodedInstruction(c),
01378 ioreg(get_A_5(opcode)),
01379 Kbit(get_reg_bit(opcode)) {}
01380
01381 int avr_op_SBIS::operator()() {
01382 int skip, clks;
01383
01384 if(core->Flash->DecodedMem[core->PC + 1]->IsInstruction2Words())
01385 skip = 3;
01386 else
01387 skip = 2;
01388
01389 if((core->GetIOReg(ioreg) & (1 << Kbit)) != 0) {
01390 core->DebugOnJump();
01391 core->PC += skip - 1;
01392 clks = skip;
01393 } else
01394 clks = 1;
01395
01396 if(core->flagXMega)
01397 clks++;
01398
01399 return clks;
01400 }
01401
01402
01403 avr_op_SBIW::avr_op_SBIW(word opcode, AvrDevice *c):
01404 DecodedInstruction(c),
01405 R1(get_rd_2(opcode)),
01406 status(c->status),
01407 K(get_K_6(opcode)) {}
01408
01409 unsigned char avr_op_SBIW::GetModifiedR() const {
01410 return R1;
01411 }
01412 unsigned char avr_op_SBIW::GetModifiedRHi() const {
01413 return R1 + 1;
01414 }
01415 int avr_op_SBIW::operator()() {
01416 byte rdl = core->GetCoreReg(R1);
01417 byte rdh = core->GetCoreReg(R1 + 1);
01418
01419 word rd = (rdh << 8) + rdl;
01420 word res = rd - K;
01421
01422 status->V = (rdh >> 7 & 0x1) & ~(res >> 15 & 0x1);
01423 status->N = (res >> 15) & 0x1;
01424 status->S = status->N ^ status->V;
01425 status->Z = (res & 0xffff) == 0;
01426 status->C = (res >> 15 & 0x1) & ~(rdh >> 7 & 0x1);
01427
01428 core->SetCoreReg(R1, res & 0xff);
01429 core->SetCoreReg(R1 + 1, (res >> 8) & 0xff);
01430
01431 return 2;
01432 }
01433
01434 avr_op_SBRC::avr_op_SBRC(word opcode, AvrDevice *c):
01435 DecodedInstruction(c),
01436 R1(get_rd_5(opcode)),
01437 Kbit(get_reg_bit(opcode)) {}
01438
01439 int avr_op_SBRC::operator()() {
01440 int skip, clks;
01441
01442 if(core->Flash->DecodedMem[core->PC + 1]->IsInstruction2Words())
01443 skip = 3;
01444 else
01445 skip = 2;
01446
01447 if((core->GetCoreReg(R1) & (1 << Kbit)) == 0) {
01448 core->DebugOnJump();
01449 core->PC += skip - 1;
01450 clks = skip;
01451 } else
01452 clks = 1;
01453
01454 return clks;
01455 }
01456
01457 avr_op_SBRS::avr_op_SBRS(word opcode, AvrDevice *c):
01458 DecodedInstruction(c),
01459 R1(get_rd_5(opcode)),
01460 Kbit(get_reg_bit(opcode)) {}
01461
01462 int avr_op_SBRS::operator()() {
01463 int skip, clks;
01464
01465 if(core->Flash->DecodedMem[core->PC + 1]->IsInstruction2Words())
01466 skip = 3;
01467 else
01468 skip = 2;
01469
01470 if((core->GetCoreReg(R1) & (1 << Kbit)) != 0) {
01471 core->DebugOnJump();
01472 core->PC += skip - 1;
01473 clks = skip;
01474 } else
01475 clks = 1;
01476
01477 return clks;
01478 }
01479
01480 avr_op_SLEEP::avr_op_SLEEP(word opcode, AvrDevice *c):
01481 DecodedInstruction(c) {}
01482
01483 int avr_op_SLEEP::operator()() {
01484 #if 0 //TODO
01485 MCUCR *mcucr = (MCUCR *)avr_core_get_vdev_by_name( core, "MCUCR" );
01486
01487 if (mcucr == NULL)
01488 avr_error( "MCUCR register not installed" );
01489
01490
01491 if ( mcucr_get_bit(mcucr, bit_SE) )
01492 {
01493 if ( mcucr_get_bit(mcucr, bit_SM) == 0 )
01494 {
01495
01496 avr_core_set_sleep_mode( core, SLEEP_MODE_IDLE);
01497 }
01498 else
01499 {
01500
01501 avr_core_set_sleep_mode( core, SLEEP_MODE_PWR_DOWN);
01502 }
01503 }
01504 #endif
01505 return 1;
01506 }
01507
01508 avr_op_SPM::avr_op_SPM(word opcode, AvrDevice *c):
01509 DecodedInstruction(c) {}
01510
01511 int avr_op_SPM::operator()() {
01512 unsigned char xaddr = 0;
01513 int cycles = 1;
01514 if(core->rampz != NULL)
01515 xaddr = core->rampz->GetRegVal();
01516 if(core->spmRegister != NULL) {
01517 unsigned int Z = core->GetRegZ();
01518 unsigned int D = core->GetCoreReg(0) + (core->GetCoreReg(1) << 8);
01519 cycles += core->spmRegister->SPM_action(D, xaddr, Z);
01520 }
01521 return cycles;
01522 }
01523
01524 avr_op_STD_Y::avr_op_STD_Y(word opcode, AvrDevice *c):
01525 DecodedInstruction(c),
01526 R1(get_rd_5(opcode)),
01527 K(get_q(opcode)) {}
01528
01529 int avr_op_STD_Y::operator()() {
01530
01531 unsigned int Y = core->GetRegY();
01532
01533 core->SetRWMem(Y + K, core->GetCoreReg(R1));
01534
01535 return (K == 0 && (core->flagXMega || core->flagTiny10)) ? 1 : 2;
01536 }
01537
01538 avr_op_STD_Z::avr_op_STD_Z(word opcode, AvrDevice *c):
01539 DecodedInstruction(c),
01540 R1(get_rd_5(opcode)),
01541 K(get_q(opcode)) {}
01542
01543 int avr_op_STD_Z::operator()() {
01544
01545 int Z = core->GetRegZ();
01546
01547 core->SetRWMem(Z + K, core->GetCoreReg(R1));
01548
01549 return (K == 0 && (core->flagXMega || core->flagTiny10)) ? 1 : 2;
01550 }
01551
01552 avr_op_STS::avr_op_STS(word opcode, AvrDevice *c):
01553 DecodedInstruction(c, true),
01554 R1(get_rd_5(opcode)) {}
01555
01556 int avr_op_STS::operator()() {
01557
01558 word k = core->Flash->ReadMemWord((core->PC + 1) * 2);
01559
01560 core->SetRWMem(k, core->GetCoreReg(R1));
01561 core->PC++;
01562
01563 return 2;
01564 }
01565
01566 avr_op_ST_X::avr_op_ST_X(word opcode, AvrDevice *c):
01567 DecodedInstruction(c),
01568 R1(get_rd_5(opcode)) {}
01569
01570 int avr_op_ST_X::operator()() {
01571
01572 word X = core->GetRegX();
01573
01574 core->SetRWMem(X, core->GetCoreReg(R1));
01575
01576 return (core->flagXMega || core->flagTiny10) ? 1 : 2;
01577 }
01578
01579 avr_op_ST_X_decr::avr_op_ST_X_decr(word opcode, AvrDevice *c):
01580 DecodedInstruction(c),
01581 R1(get_rd_5(opcode)) {}
01582
01583 int avr_op_ST_X_decr::operator()() {
01584
01585 word X = core->GetRegX();
01586 if (R1 == 26 || R1 == 27)
01587 avr_error( "Result of operation is undefined" );
01588
01589
01590 X--;
01591 core->SetCoreReg(26, X & 0xff);
01592 core->SetCoreReg(27, (X >> 8) & 0xff);
01593 core->SetRWMem(X, core->GetCoreReg(R1));
01594
01595 return 2;
01596 }
01597
01598 avr_op_ST_X_incr::avr_op_ST_X_incr(word opcode, AvrDevice *c):
01599 DecodedInstruction(c),
01600 R1(get_rd_5(opcode)) {}
01601
01602 int avr_op_ST_X_incr::operator()() {
01603
01604 word X = core->GetRegX();
01605 if (R1 == 26 || R1 == 27)
01606 avr_error( "Result of operation is undefined" );
01607
01608 core->SetRWMem(X, core->GetCoreReg(R1));
01609
01610
01611 X++;
01612 core->SetCoreReg(26, X & 0xff);
01613 core->SetCoreReg(27, (X >> 8) & 0xff);
01614
01615 return (core->flagXMega || core->flagTiny10) ? 1 : 2;
01616 }
01617
01618 avr_op_ST_Y_decr::avr_op_ST_Y_decr(word opcode, AvrDevice *c):
01619 DecodedInstruction(c),
01620 R1(get_rd_5(opcode)) {}
01621
01622 int avr_op_ST_Y_decr::operator()() {
01623
01624 word Y = core->GetRegY();
01625 if (R1 == 28 || R1 == 29)
01626 avr_error( "Result of operation is undefined" );
01627
01628
01629 Y--;
01630 core->SetCoreReg(28, Y & 0xff);
01631 core->SetCoreReg(29, (Y >> 8) & 0xff);
01632 core->SetRWMem(Y, core->GetCoreReg(R1));
01633
01634 return 2;
01635 }
01636
01637 avr_op_ST_Y_incr::avr_op_ST_Y_incr(word opcode, AvrDevice *c):
01638 DecodedInstruction(c),
01639 R1(get_rd_5(opcode)) {}
01640
01641 int avr_op_ST_Y_incr::operator()() {
01642
01643 word Y = core->GetRegY();
01644 if (R1 == 28 || R1 == 29)
01645 avr_error( "Result of operation is undefined" );
01646
01647 core->SetRWMem(Y, core->GetCoreReg(R1));
01648
01649
01650 Y++;
01651 core->SetCoreReg(28, Y & 0xff);
01652 core->SetCoreReg(29, (Y >> 8) & 0xff);
01653
01654 return (core->flagXMega || core->flagTiny10) ? 1 : 2;
01655 }
01656
01657 avr_op_ST_Z_decr::avr_op_ST_Z_decr(word opcode, AvrDevice *c):
01658 DecodedInstruction(c),
01659 R1(get_rd_5(opcode)) {}
01660
01661 int avr_op_ST_Z_decr::operator()() {
01662
01663 word Z = core->GetRegZ();
01664 if (R1 == 30 || R1 == 31)
01665 avr_error( "Result of operation is undefined" );
01666
01667
01668 Z--;
01669 core->SetCoreReg(30, Z & 0xff);
01670 core->SetCoreReg(31, (Z >> 8) & 0xff);
01671 core->SetRWMem(Z, core->GetCoreReg(R1));
01672
01673 return 2;
01674 }
01675
01676 avr_op_ST_Z_incr::avr_op_ST_Z_incr(word opcode, AvrDevice *c):
01677 DecodedInstruction(c),
01678 R1(get_rd_5(opcode)) {}
01679
01680 int avr_op_ST_Z_incr::operator()() {
01681
01682 word Z = core->GetRegZ();
01683 if (R1 == 30 || R1 == 31)
01684 avr_error( "Result of operation is undefined" );
01685
01686 core->SetRWMem(Z, core->GetCoreReg(R1));
01687
01688
01689 Z++;
01690 core->SetCoreReg(30, Z & 0xff);
01691 core->SetCoreReg(31, (Z >> 8) & 0xff);
01692
01693 return (core->flagXMega || core->flagTiny10) ? 1 : 2;
01694 }
01695
01696 avr_op_SUB::avr_op_SUB(word opcode, AvrDevice *c):
01697 DecodedInstruction(c),
01698 R1(get_rd_5(opcode)),
01699 R2(get_rr_5(opcode)),
01700 status(c->status) {}
01701
01702 unsigned char avr_op_SUB::GetModifiedR() const {
01703 return R1;
01704 }
01705 int avr_op_SUB::operator()() {
01706 byte rd = core->GetCoreReg(R1);
01707 byte rr = core->GetCoreReg(R2);
01708
01709 byte res = rd - rr;
01710
01711 status->H = get_sub_carry(res, rd, rr, 3);
01712 status->V = get_sub_overflow(res, rd, rr);
01713 status->N = (res >> 7) & 0x1;
01714 status->S = status->N ^ status->V;
01715 status->Z = (res & 0xff) == 0;
01716 status->C = get_sub_carry(res, rd, rr, 7);
01717
01718 core->SetCoreReg(R1, res);
01719
01720 return 1;
01721 }
01722
01723 avr_op_SUBI::avr_op_SUBI(word opcode, AvrDevice *c):
01724 DecodedInstruction(c),
01725 R1(get_rd_4(opcode)),
01726 status(c->status),
01727 K(get_K_8(opcode)) {}
01728
01729 unsigned char avr_op_SUBI::GetModifiedR() const {
01730 return R1;
01731 }
01732 int avr_op_SUBI::operator()() {
01733 byte rd = core->GetCoreReg(R1);
01734 byte res = rd - K;
01735
01736 status->H = get_sub_carry(res, rd, K, 3);
01737 status->V = get_sub_overflow(res, rd, K);
01738 status->N = (res >> 7) & 0x1;
01739 status->S = status->N ^ status->V;
01740 status->Z = (res & 0xff) == 0;
01741 status->C = get_sub_carry(res, rd, K, 7);
01742
01743 core->SetCoreReg(R1, res);
01744
01745 return 1;
01746 }
01747
01748 avr_op_SWAP::avr_op_SWAP(word opcode, AvrDevice *c):
01749 DecodedInstruction(c),
01750 R1(get_rd_5(opcode)) {}
01751
01752 int avr_op_SWAP::operator()() {
01753 byte rd = core->GetCoreReg(R1);
01754 byte res = ((rd << 4) & 0xf0) | ((rd >> 4) & 0x0f);
01755
01756 core->SetCoreReg(R1, res);
01757
01758 return 1;
01759 }
01760
01761 avr_op_WDR::avr_op_WDR(word opcode, AvrDevice *c):
01762 DecodedInstruction(c) {}
01763
01764 int avr_op_WDR::operator()() {
01765 if(core->wado != NULL)
01766 core->wado->Wdr();
01767
01768 return 1;
01769 }
01770
01771 avr_op_BREAK::avr_op_BREAK(word opcode, AvrDevice *c):
01772 DecodedInstruction(c) {}
01773
01774 int avr_op_BREAK::operator()() {
01775 return BREAK_POINT+1;
01776 }
01777
01778 avr_op_ILLEGAL::avr_op_ILLEGAL(word opcode, AvrDevice *c):
01779 DecodedInstruction(c) {}
01780
01781 int avr_op_ILLEGAL::operator()() {
01782 avr_error("Illegal opcode '%02x %02x' executed at PC=0x%x (%d)! Simulation terminated!",
01783 core->Flash->myMemory[core->PC*2+1], core->Flash->myMemory[core->PC*2], core->PC*2, core->PC);
01784 return 0;
01785 }
01786
01787 static int get_add_carry( byte res, byte rd, byte rr, int b )
01788 {
01789 byte resb = res >> b & 0x1;
01790 byte rdb = rd >> b & 0x1;
01791 byte rrb = rr >> b & 0x1;
01792 return (rdb & rrb) | (rrb & ~resb) | (~resb & rdb);
01793 }
01794
01795 static int get_add_overflow( byte res, byte rd, byte rr )
01796 {
01797 byte res7 = res >> 7 & 0x1;
01798 byte rd7 = rd >> 7 & 0x1;
01799 byte rr7 = rr >> 7 & 0x1;
01800 return (rd7 & rr7 & ~res7) | (~rd7 & ~rr7 & res7);
01801 }
01802
01803 static int get_sub_carry( byte res, byte rd, byte rr, int b )
01804 {
01805 byte resb = res >> b & 0x1;
01806 byte rdb = rd >> b & 0x1;
01807 byte rrb = rr >> b & 0x1;
01808 return (~rdb & rrb) | (rrb & resb) | (resb & ~rdb);
01809 }
01810
01811 static int get_sub_overflow( byte res, byte rd, byte rr )
01812 {
01813 byte res7 = res >> 7 & 0x1;
01814 byte rd7 = rd >> 7 & 0x1;
01815 byte rr7 = rr >> 7 & 0x1;
01816 return (rd7 & ~rr7 & ~res7) | (~rd7 & rr7 & res7);
01817 }
01818
01819 static int get_compare_carry( byte res, byte rd, byte rr, int b )
01820 {
01821 byte resb = res >> b & 0x1;
01822 byte rdb = rd >> b & 0x1;
01823 byte rrb = rr >> b & 0x1;
01824 return (~rdb & rrb) | (rrb & resb) | (resb & ~rdb);
01825 }
01826
01827 static int get_compare_overflow( byte res, byte rd, byte rr )
01828 {
01829 byte res7 = res >> 7 & 0x1;
01830 byte rd7 = rd >> 7 & 0x1;
01831 byte rr7 = rr >> 7 & 0x1;
01832
01833
01834 return (rd7 & ~rr7 & ~res7) | (~rd7 & rr7 & res7);
01835 }
01836 static int n_bit_unsigned_to_signed( unsigned int val, int n )
01837 {
01838
01839 unsigned int mask;
01840
01841 if ( (val & (1 << (n-1))) == 0)
01842 return (int)val;
01843
01844
01845 mask = (1 << n) - 1;
01846 return -1 * ((~val & mask) + 1);
01847 }
01848
01849
01850 static int get_rd_2( word opcode )
01851 {
01852 int reg = ((opcode & mask_Rd_2) >> 4) & 0x3;
01853 return (reg * 2) + 24;
01854 }
01855
01856 static int get_rd_3( word opcode )
01857 {
01858 int reg = opcode & mask_Rd_3;
01859 return ((reg >> 4) & 0x7) + 16;
01860 }
01861
01862 static int get_rd_4( word opcode )
01863 {
01864 int reg = opcode & mask_Rd_4;
01865 return ((reg >> 4) & 0xf) + 16;
01866 }
01867
01868 static int get_rd_5( word opcode )
01869 {
01870 int reg = opcode & mask_Rd_5;
01871 return ((reg >> 4) & 0x1f);
01872 }
01873
01874 static int get_rr_3( word opcode )
01875 {
01876 return (opcode & mask_Rr_3) + 16;
01877 }
01878
01879 static int get_rr_4( word opcode )
01880 {
01881 return (opcode & mask_Rr_4) + 16;
01882 }
01883
01884 static int get_rr_5( word opcode )
01885 {
01886 int reg = opcode & mask_Rr_5;
01887 return (reg & 0xf) + ((reg >> 5) & 0x10);
01888 }
01889
01890 static byte get_K_8( word opcode )
01891 {
01892 int K = opcode & mask_K_8;
01893 return ((K >> 4) & 0xf0) + (K & 0xf);
01894 }
01895
01896 static byte get_K_6( word opcode )
01897 {
01898 int K = opcode & mask_K_6;
01899 return ((K >> 2) & 0x0030) + (K & 0xf);
01900 }
01901
01902 static int get_k_7( word opcode )
01903 {
01904 return (((opcode & mask_k_7) >> 3) & 0x7f);
01905 }
01906
01907 static int get_k_12( word opcode )
01908 {
01909 return (opcode & mask_k_12);
01910 }
01911
01912 static int get_k_22( word opcode )
01913 {
01914
01915
01916
01917
01918
01919 int k = opcode & mask_k_22;
01920 return ((k >> 3) & 0x003e) + (k & 0x1);
01921 }
01922
01923 static int get_reg_bit( word opcode )
01924 {
01925 return opcode & mask_reg_bit;
01926 }
01927
01928 static int get_sreg_bit( word opcode )
01929 {
01930 return (opcode & mask_sreg_bit) >> 4;
01931 }
01932
01933 static int get_q( word opcode )
01934 {
01935
01936 int q = opcode & mask_q_displ;
01937 int qq = ( ((q >> 1) & 0x1000) + (q & 0x0c00) ) >> 7;
01938 return (qq & 0x0038) + (q & 0x7);
01939 }
01940
01941 static int get_A_5( word opcode )
01942 {
01943 return (opcode & mask_A_5) >> 3;
01944 }
01945
01946 static int get_A_6( word opcode )
01947 {
01948 int A = opcode & mask_A_6;
01949 return ((A >> 5) & 0x0030) + (A & 0xf);
01950 }
01951
01952
01953
01954
01955 DecodedInstruction* lookup_opcode( word opcode, AvrDevice *core )
01956 {
01957 int decode;
01958
01959 switch (opcode) {
01960
01961 case 0x9519:
01962 if(core->flagEIJMPInstructions)
01963 return new avr_op_EICALL(opcode, core);
01964 else
01965 return new avr_op_ILLEGAL(opcode, core);
01966 case 0x9419:
01967 if(core->flagEIJMPInstructions)
01968 return new avr_op_EIJMP(opcode, core);
01969 else
01970 return new avr_op_ILLEGAL(opcode, core);
01971 case 0x95D8:
01972 if(core->flagELPMInstructions)
01973 return new avr_op_ELPM(opcode, core);
01974 else
01975 return new avr_op_ILLEGAL(opcode, core);
01976 case 0x95F8:
01977 if(core->flagLPMInstructions)
01978 return new avr_op_ESPM(opcode, core);
01979 else
01980 return new avr_op_ILLEGAL(opcode, core);
01981 case 0x9509:
01982 if(core->flagIJMPInstructions)
01983 return new avr_op_ICALL(opcode, core);
01984 else
01985 return new avr_op_ILLEGAL(opcode, core);
01986 case 0x9409:
01987 if(core->flagIJMPInstructions)
01988 return new avr_op_IJMP(opcode, core);
01989 else
01990 return new avr_op_ILLEGAL(opcode, core);
01991 case 0x95C8:
01992 if(!core->flagTiny10)
01993
01994 return new avr_op_LPM(opcode, core);
01995 else
01996 return new avr_op_ILLEGAL(opcode, core);
01997 case 0x0000: return new avr_op_NOP(opcode, core);
01998 case 0x9508: return new avr_op_RET(opcode, core);
01999 case 0x9518: return new avr_op_RETI(opcode, core);
02000 case 0x9588: return new avr_op_SLEEP(opcode, core);
02001 case 0x95E8:
02002 if(core->flagLPMInstructions)
02003 return new avr_op_SPM(opcode, core);
02004 else
02005 return new avr_op_ILLEGAL(opcode, core);
02006 case 0x95A8: return new avr_op_WDR(opcode, core);
02007 case 0x9598: return new avr_op_BREAK(opcode, core);
02008 default:
02009 {
02010
02011 decode = opcode & ~(mask_Rd_5 | mask_Rr_5);
02012 switch ( decode ) {
02013 case 0x1C00: return new avr_op_ADC(opcode, core);
02014 case 0x0C00: return new avr_op_ADD(opcode, core);
02015 case 0x2000: return new avr_op_AND(opcode, core);
02016 case 0x1400: return new avr_op_CP(opcode, core);
02017 case 0x0400: return new avr_op_CPC(opcode, core);
02018 case 0x1000: return new avr_op_CPSE(opcode, core);
02019 case 0x2400: return new avr_op_EOR(opcode, core);
02020 case 0x2C00: return new avr_op_MOV(opcode, core);
02021 case 0x9C00:
02022 if(core->flagMULInstructions)
02023 return new avr_op_MUL(opcode, core);
02024 else
02025 return new avr_op_ILLEGAL(opcode, core);
02026 case 0x2800: return new avr_op_OR(opcode, core);
02027 case 0x0800: return new avr_op_SBC(opcode, core);
02028 case 0x1800: return new avr_op_SUB(opcode, core);
02029 }
02030
02031
02032 decode = opcode & ~(mask_Rd_5);
02033 switch (decode) {
02034 case 0x9405: return new avr_op_ASR(opcode, core);
02035 case 0x9400: return new avr_op_COM(opcode, core);
02036 case 0x940A: return new avr_op_DEC(opcode, core);
02037 case 0x9006:
02038 if(core->flagELPMInstructions)
02039 return new avr_op_ELPM_Z(opcode, core);
02040 else
02041 return new avr_op_ILLEGAL(opcode, core);
02042 case 0x9007:
02043 if(core->flagELPMInstructions)
02044 return new avr_op_ELPM_Z_incr(opcode, core);
02045 else
02046 return new avr_op_ILLEGAL(opcode, core);
02047 case 0x9403: return new avr_op_INC(opcode, core);
02048 case 0x9000: return new avr_op_LDS(opcode, core);
02049 case 0x900C:
02050 if(!core->flagTiny1x)
02051 return new avr_op_LD_X(opcode, core);
02052 else
02053 return new avr_op_ILLEGAL(opcode, core);
02054 case 0x900E:
02055 if(!core->flagTiny1x)
02056 return new avr_op_LD_X_decr(opcode, core);
02057 else
02058 return new avr_op_ILLEGAL(opcode, core);
02059 case 0x900D:
02060 if(!core->flagTiny1x)
02061 return new avr_op_LD_X_incr(opcode, core);
02062 else
02063 return new avr_op_ILLEGAL(opcode, core);
02064 case 0x8008:
02065 if(!core->flagTiny1x)
02066 return new avr_op_LDD_Y(opcode, core);
02067 else
02068 return new avr_op_ILLEGAL(opcode, core);
02069 case 0x900A:
02070 if(!core->flagTiny1x)
02071 return new avr_op_LD_Y_decr(opcode, core);
02072 else
02073 return new avr_op_ILLEGAL(opcode, core);
02074 case 0x9009:
02075 if(!core->flagTiny1x)
02076 return new avr_op_LD_Y_incr(opcode, core);
02077 else
02078 return new avr_op_ILLEGAL(opcode, core);
02079 case 0x8000: return new avr_op_LDD_Z(opcode, core);
02080 case 0x9002:
02081 if(!core->flagTiny1x)
02082 return new avr_op_LD_Z_decr(opcode, core);
02083 else
02084 return new avr_op_ILLEGAL(opcode, core);
02085 case 0x9001:
02086 if(!core->flagTiny1x)
02087 return new avr_op_LD_Z_incr(opcode, core);
02088 else
02089 return new avr_op_ILLEGAL(opcode, core);
02090 case 0x9004:
02091 if(core->flagLPMInstructions)
02092 return new avr_op_LPM_Z(opcode, core);
02093 else
02094 return new avr_op_ILLEGAL(opcode, core);
02095 case 0x9005:
02096 if(core->flagLPMInstructions)
02097 return new avr_op_LPM_Z_incr(opcode, core);
02098 else
02099 return new avr_op_ILLEGAL(opcode, core);
02100 case 0x9406: return new avr_op_LSR(opcode, core);
02101 case 0x9401: return new avr_op_NEG(opcode, core);
02102 case 0x900F:
02103 if(!core->flagTiny1x)
02104 return new avr_op_POP(opcode, core);
02105 else
02106 return new avr_op_ILLEGAL(opcode, core);
02107 case 0x920F:
02108 if(!core->flagTiny1x)
02109 return new avr_op_PUSH(opcode, core);
02110 else
02111 return new avr_op_ILLEGAL(opcode, core);
02112 case 0x9407: return new avr_op_ROR(opcode, core);
02113 case 0x9200: return new avr_op_STS(opcode, core);
02114 case 0x920C:
02115 if(!core->flagTiny1x)
02116 return new avr_op_ST_X(opcode, core);
02117 case 0x920E:
02118 if(!core->flagTiny1x)
02119 return new avr_op_ST_X_decr(opcode, core);
02120 else
02121 return new avr_op_ILLEGAL(opcode, core);
02122 case 0x920D:
02123 if(!core->flagTiny1x)
02124 return new avr_op_ST_X_incr(opcode, core);
02125 else
02126 return new avr_op_ILLEGAL(opcode, core);
02127 case 0x8208:
02128 if(!core->flagTiny1x)
02129 return new avr_op_STD_Y(opcode, core);
02130 else
02131 return new avr_op_ILLEGAL(opcode, core);
02132 case 0x920A:
02133 if(!core->flagTiny1x)
02134 return new avr_op_ST_Y_decr(opcode, core);
02135 else
02136 return new avr_op_ILLEGAL(opcode, core);
02137 case 0x9209:
02138 if(!core->flagTiny1x)
02139 return new avr_op_ST_Y_incr(opcode, core);
02140 else
02141 return new avr_op_ILLEGAL(opcode, core);
02142 case 0x8200: return new avr_op_STD_Z(opcode, core);
02143 case 0x9202:
02144 if(!core->flagTiny1x)
02145 return new avr_op_ST_Z_decr(opcode, core);
02146 else
02147 return new avr_op_ILLEGAL(opcode, core);
02148 case 0x9201:
02149 if(!core->flagTiny1x)
02150 return new avr_op_ST_Z_incr(opcode, core);
02151 else
02152 return new avr_op_ILLEGAL(opcode, core);
02153 case 0x9402: return new avr_op_SWAP(opcode, core);
02154 }
02155
02156
02157 decode = opcode & ~(mask_Rd_4 | mask_K_8);
02158 switch ( decode ) {
02159 case 0x7000: return new avr_op_ANDI(opcode, core);
02160 case 0x3000: return new avr_op_CPI(opcode, core);
02161 case 0xE000: return new avr_op_LDI(opcode, core);
02162 case 0x6000: return new avr_op_ORI(opcode, core);
02163 case 0x4000: return new avr_op_SBCI(opcode, core);
02164 case 0x5000: return new avr_op_SUBI(opcode, core);
02165 }
02166
02167
02168 decode = opcode & ~(mask_Rd_5 | mask_reg_bit);
02169 switch ( decode ) {
02170 case 0xF800: return new avr_op_BLD(opcode, core);
02171 case 0xFA00: return new avr_op_BST(opcode, core);
02172 case 0xFC00: return new avr_op_SBRC(opcode, core);
02173 case 0xFE00: return new avr_op_SBRS(opcode, core);
02174 }
02175
02176
02177 decode = opcode & ~(mask_k_7 | mask_reg_bit);
02178 switch ( decode ) {
02179 case 0xF400: return new avr_op_BRBC(opcode, core);
02180 case 0xF000: return new avr_op_BRBS(opcode, core);
02181 }
02182
02183
02184 if(!core->flagTiny10 && !core->flagTiny1x) {
02185 decode = opcode & ~(mask_Rd_5 | mask_q_displ);
02186 switch ( decode ) {
02187 case 0x8008: return new avr_op_LDD_Y(opcode, core);
02188 case 0x8000: return new avr_op_LDD_Z(opcode, core);
02189 case 0x8208: return new avr_op_STD_Y(opcode, core);
02190 case 0x8200: return new avr_op_STD_Z(opcode, core);
02191 }
02192 }
02193
02194
02195 decode = opcode & ~(mask_k_22);
02196 switch ( decode ) {
02197 case 0x940E:
02198 if(core->flagJMPInstructions)
02199 return new avr_op_CALL(opcode, core);
02200 else
02201 return new avr_op_ILLEGAL(opcode, core);
02202 case 0x940C:
02203 if(core->flagJMPInstructions)
02204 return new avr_op_JMP(opcode, core);
02205 else
02206 return new avr_op_ILLEGAL(opcode, core);
02207 }
02208
02209
02210 decode = opcode & ~(mask_sreg_bit);
02211 switch ( decode ) {
02212
02213
02214 case 0x9488: return new avr_op_BCLR(opcode, core);
02215 case 0x9408: return new avr_op_BSET(opcode, core);
02216 }
02217
02218
02219 decode = opcode & ~(mask_K_6 | mask_Rd_2);
02220 switch ( decode ) {
02221 case 0x9600:
02222 if(core->flagIWInstructions)
02223 return new avr_op_ADIW(opcode, core);
02224 else
02225 return new avr_op_ILLEGAL(opcode, core);
02226 case 0x9700:
02227 if(core->flagIWInstructions)
02228 return new avr_op_SBIW(opcode, core);
02229 else
02230 return new avr_op_ILLEGAL(opcode, core);
02231 }
02232
02233
02234 decode = opcode & ~(mask_A_5 | mask_reg_bit);
02235 switch ( decode ) {
02236 case 0x9800: return new avr_op_CBI(opcode, core);
02237 case 0x9A00: return new avr_op_SBI(opcode, core);
02238 case 0x9900: return new avr_op_SBIC(opcode, core);
02239 case 0x9B00: return new avr_op_SBIS(opcode, core);
02240 }
02241
02242
02243 decode = opcode & ~(mask_A_6 | mask_Rd_5);
02244 switch ( decode ) {
02245 case 0xB000: return new avr_op_IN(opcode, core);
02246 case 0xB800: return new avr_op_OUT(opcode, core);
02247 }
02248
02249
02250 decode = opcode & ~(mask_k_12);
02251 switch ( decode ) {
02252 case 0xD000: return new avr_op_RCALL(opcode, core);
02253 case 0xC000: return new avr_op_RJMP(opcode, core);
02254 }
02255
02256
02257 decode = opcode & ~(mask_Rd_4 | mask_Rr_4);
02258 switch ( decode ) {
02259 case 0x0100:
02260 if(core->flagMOVWInstruction)
02261 return new avr_op_MOVW(opcode, core);
02262 else
02263 return new avr_op_ILLEGAL(opcode, core);
02264 case 0x0200:
02265 if(core->flagMULInstructions)
02266 return new avr_op_MULS(opcode, core);
02267 else
02268 return new avr_op_ILLEGAL(opcode, core);
02269 }
02270
02271
02272 decode = opcode & ~(mask_Rd_3 | mask_Rr_3);
02273 switch ( decode ) {
02274 case 0x0300:
02275 if(core->flagMULInstructions)
02276 return new avr_op_MULSU(opcode, core);
02277 else
02278 return new avr_op_ILLEGAL(opcode, core);
02279 case 0x0308:
02280 if(core->flagMULInstructions)
02281 return new avr_op_FMUL(opcode, core);
02282 else
02283 return new avr_op_ILLEGAL(opcode, core);
02284 case 0x0380:
02285 if(core->flagMULInstructions)
02286 return new avr_op_FMULS(opcode, core);
02287 else
02288 return new avr_op_ILLEGAL(opcode, core);
02289 case 0x0388:
02290 if(core->flagMULInstructions)
02291 return new avr_op_FMULSU(opcode, core);
02292 else
02293 return new avr_op_ILLEGAL(opcode, core);
02294 }
02295
02296 }
02297 }
02298
02299
02300 return new avr_op_ILLEGAL(opcode, core);
02301
02302 }
02303